ct_pmp_regs design specification

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1. Introduction:

  • Module Name: ct_pmp_regs

  • Module Overview: The ct_pmp_regs module is designed to manage and configure a set of registers related to physical memory protection (PMP) in a processor. The primary objective of this module is to handle the read and write operations to PMP configuration and address registers. It ensures that the PMP settings are correctly updated based on control signals, allowing for secure and controlled access to memory regions. The module supports multiple PMP entries, each with configurable attributes such as read, write, execute permissions, address mode, and lock status.

  • Timing control:

2. Input/Output Interfaces Descriptions:

  • Inputs:

    • cp0_pmp_wdata [63:0]: A 64-bit data bus used to write data into the PMP configuration and address registers.
    • cpuclk: The clock signal for synchronizing operations within the module.
    • cpurst_b: An active-low reset signal used to initialize the module’s registers to their default states.
    • pmp_csr_sel [17:0]: An 18-bit signal used to select which PMP configuration or address register is being accessed.
    • pmp_csr_wen [17:0]: An 18-bit write enable signal used to control the write operations to the PMP registers.

  • Outputs:

    • pmp_cp0_data [63:0]: A 64-bit data bus used to output data from the PMP configuration and address registers.
    • pmpaddr0_value [28:0] to pmpaddr7_value [28:0]: Eight 29-bit signals representing the values of the PMP address registers.
    • pmpcfg0_value [63:0]: A 64-bit signal representing the combined values of the first four PMP configuration registers.
    • pmpcfg2_value [63:0]: A 64-bit signal representing the combined values of the next four PMP configuration registers.

3. Clock and Reset Strategy:

  • Clock:

    • Name: cpuclk
    • Active State: The clock signal is active on the rising edge, which is used to synchronize all sequential logic within the module.

  • Reset:

    • Name: cpurst_b
    • Active State: The reset signal is active-low. When asserted (logic 0), it initializes all PMP configuration and address registers to their default states, ensuring a known starting condition for the module.

4-1. Parameters constant:

The module contains the following parameter constant:

  • parameter ADDR_WIDTH = 29;

4-2. Macro constant:

  • None

5. Algorithmic Logic

  1. Configuration Registers:

    • The module contains multiple configuration registers (pmpcfg) which store permissions and attributes such as readable, writable, executable, and locked states.
    • Each configuration register manages separate regions or segments of memory, with specific fields determining the operation mode and permissions of each segment.

  2. PMP Initialization:

    • Upon reset (cpurst_b signal low), all the configuration and address registers within the module are initialized to a predefined state (0), ensuring a secure and known initial state.

  3. Permission and Mode Settings:

    • Each PMP configuration register (pmpcfgX) holds bits that define access rights: readable, writable, and executable, alongside a two-bit mode for address matching.
    • The lock bit in each configuration register indicates whether further writes to the register are possible.

  4. Hardware Updates:

    • Configuration registers are updated on the rising edge of the clock (cpuclk) when the corresponding write enable (pmp_csr_wen) signals are valid and no lock conditions are met.
    • Address registers are updated similarly, respecting any lock and match-mode dependencies ensuring secure modification prevention.

  5. Chaining Logic:

    • Address matching and permission interpretation rely on the state of the configuration registers, such as mode matching and lock conditions.
    • For chained configurations, the write operations to a PMP address are conditional on already established locks and address mode values.

  6. Inter-module Communication:

    • Input cp0_pmp_wdata carries the data for register updates, while pmp_cp0_data serves as an output conveying PMP configurations to other modules.
    • Selection and enable vectors (pmp_csr_sel, pmp_csr_wen) control which registers are accessed for read/write operations.

6 Operational Cycles

  • Reset Phase: Registers are reset, meaning they all initialize to zero, ensuring that all regions are initially inaccessible until explicitly configured.

  • Configuration Phase: During normal operation post-reset, configuration registers can be updated based on provided data (cp0_pmp_wdata) when writing is enabled via control signals and existing register contents permit the modification (e.g., no active lock bits).

  • Normal Operation: During normal runtime, the PMP registers govern access permissions dynamically, allowing secure and managed access to the processor’s memory space per the configuration stored within these registers.
    Algorithm Mechanics:

  • Registers: The module contains various configuration registers (pmp0cfg, pmp1cfg, … , pmp7cfg) and address registers (pmpaddr0_value through pmpaddr7_value) to manage PMP regions.

  • Configuration Logic:

    • Each pmpcfg# register has fields for address matching mode, permissions (readable, writable, executable), and a lock bit to prevent further modifications.
    • Data from cp0_pmp_wdata is loaded into registers based on write enable signals (pmp_csr_wen[]) provided that the lock bit is not set.

  • Address Logic:

    • Address registers are updated based on corresponding enable signals ensuring the previous entry is not locked.

Timing: Updates to the registers are synchronized with the clock signal. On a rising edge of cpuclk, updates occur if the write enable (pmp_csr_wen[]) is set and the reset (cpurst_b) is not asserted.

7. Data Flow

Data Tracing and Processing:

  • Input to Register Update: Data from cp0_pmp_wdata is stored into the appropriate configuration (pmpcfg#) or address (pmpaddr#_value) register based on the current state of selection and enable signals, considering lock conditions.
  • Configuration to Output: The corresponding configuration or address states can be read out via pmp_cp0_data or pmpcfg0_value, based on pmp_csr_sel[].

Error Handling:

  • Lock Protection: If a lock bit within a configuration register is set, further writes to that configuration are blocked regardless of the enable state.

Timing in Data Movement:

  • Sequential Updates: Data from cp0_pmp_wdata is sequentially applied across cycles, starting with the first enabled register according to the selection and enable signals.

Concurrency Management:

  • Independent Configuration Blocks: Each pmpcfg# and pmpaddr# register set operates independently, allowing updates to different regions concurrently, as long as they adhere to lock and enable conditions.