ahb_sfr design specification

1. Introduction:

• Module Name: ahb_sfr

• Module Overview: The ahb_sfr module is designed to interface with a system’s Special Function Registers (SFRs) via the AHB (Advanced High-performance Bus). It primarily handles the reading and writing operations to these registers based on external requests. The module synchronizes these requests and manages data transfer between the external bus and the internal registers, ensuring data integrity and proper timing.

• Timing control:

2. Input/Output Interfaces Descriptions:

• Inputs:

  • sfrclk: The clock signal for the module. All synchronous operations are triggered on the rising edge of this clock.
  • sfrrstz: Active low reset signal. When asserted, it initializes the module’s internal registers and logic.
  • sfrdatai [7:0]: Data input from the SFRs to be sent to the external bus.
  • ADDR [14:0]: Address bus input specifying the SFR address for the current operation.
  • DATA [7:0]: Data bus input specifying the data to be written to the SFRs.
  • REQ: Request signal indicating an active read or write operation.
  • WR: Write enable signal indicating if the current operation is a write (asserted) or read (deasserted).

• Outputs:

  • sfrwe: Write enable output that signals whether a write operation should be performed to the SFRs.
  • sfraddr (output wire [14:0]): Address output that mirrors the input address to the SFRs.
  • sfrdatao [7:0]: Data output holding the data to be written to the SFRs.
  • s2adata [7:0]: Data output that directly mirrors the input sfrdatai, intended for external monitoring or further processing.
  • ACK: Acknowledge signal toggled to indicate the completion of a request processing cycle.

3. Clock and Reset Strategy:

• Clock:

  • Name: sfrclk
  • Active State: The clock signal is active on the rising edge, which is used to synchronize all sequential logic within the module.

• Reset:

  • Name: sfrrstz
  • Active State: The reset signal is active-low. When asserted, it initializes the module’s internal registers and logic.

4-1. Parameters constant:

• None

4-2. Macro constant:

• None

5. Algorithmic Logic

• Reset and Initialization:
  All internal registers (ReqSyncD, SFRWrS, data_i, wr_i, addr_i, sfrwe, sfrdatao, and ACK) are initialized to their default states upon reset (sfrrstz asserted).

• Request Synchronization:
  The module uses a simple synchronization mechanism to detect edges in the REQ signal. This is achieved by comparing the current REQ state with a delayed version (ReqSyncD), stored from the previous clock cycle. The result (ReqToggle) indicates a change in the request state, triggering data and control updates.

• Data and Control Flow:
  Upon detecting a request (ReqToggle asserted), the module captures the address (ADDR), data (DATA), and write enable (WR) from the inputs and stores them in internal registers (addr_i, data_i, wr_i). These values are used to set up the subsequent operations.

  • If a write operation is detected (wr_i asserted), the write enable output (sfrwe) is set based on the SFRWrS status, which tracks the request state to prevent erroneous writes during request transitions.
  • For write operations, the data to be written to the SFR (sfrdatao) is updated with the value from data_i if both wr_i and SFRWrS are asserted.

• Output and Acknowledgement:
  The address output (sfraddr) directly mirrors the internal address register (addr_i). The s2adata output is a direct pass-through of the sfrdatai input, allowing external entities to monitor or process the incoming SFR data. The ACK signal is toggled to indicate the completion of a processing cycle, helping external controllers to manage the timing and sequence of operations.

6 Operational Cycles

The ahb_sfr module is designed to interface with a system bus, handling specific register operations including data transfer and synchronization. The module operates primarily on the rising edge of the system clock (sfrclk) and remains sensitive to the active low reset signal (sfrrstz). The core functionality revolves around capturing and responding to data requests from the bus, managing data write operations, and acknowledging the completion of these operations.

Sequential Logic:

• Reset and Synchronization: The module uses edge-triggered flip-flops to capture and synchronize the request signal (REQ). This synchronization helps in mitigating any metastability issues due to the asynchronous nature of the input request.
• Data and Control Signal Capturing: Upon detecting a change in the request signal (ReqToggle), the module captures the address (ADDR), data (DATA), and write control signal (WR) from the bus. These captured values are stored in internal registers (addr_i, data_i, wr_i) and are used in subsequent operations.
• Write Enable Logic: The write enable signal (sfrwe) is controlled based on the write request (wr_i) and the synchronization status (SFRWrS). This ensures that write operations are only enabled under valid conditions.
• Data Output and Acknowledgment: The module outputs data (sfrdatao) and toggles the acknowledgment signal (ACK) based on the internal state and the synchronization of the request.

Combinational Logic:

• Request Toggle Detection: A simple XOR gate detects changes in the request signal, generating a toggle signal (ReqToggle) that triggers data capturing and acknowledgment logic.
• Data Output to System Bus: The output data to the system bus (s2adata) is directly driven by the input data from another source (sfrdatai), indicating a simple combinational pathway.

7. Data Flow

• ReqSyncD (Request Synchronized Delayed): This signal holds the delayed version of the external request signal (REQ). It is used to detect edges in the request signal by comparing its current state to its previous state.
• data_i (Data Input Register): Captures the data from the bus when a new request is detected. This register temporarily holds the data for processing or forwarding during the write operations.
• SFRWrS (SFR Write Synchronize): Indicates the synchronization status for write operations. It is set when a new request is detected and used to control the write enable signal.
• wr_i (Write Input Register): Captures the write control signal from the bus, indicating whether the current operation involves writing data to the register.
• addr_i (Address Input Register): Holds the address from the bus where data needs to be written or read, captured upon a new request.
• ReqToggle (Request Toggle): A signal generated by XORing the current and delayed request signals. It indicates a change in the request status, used to trigger data capturing and acknowledgment logic.
• sfrwe (SFR Write Enable): Controlled by the write request and synchronization status, this signal enables the data write operation to the internal registers.
• sfrdatao (SFR Data Output): Outputs data based on the internal logic conditions, specifically during write operations when both write request and synchronization are affirmed.
• ACK (Acknowledgment): Toggled in response to a new request detection, signaling the completion of a data read or write operation.