if [ -f ~/.bash_aliases ]; then . ~/.bash_aliases fi
# enable programmable completion features (you don't need to enable # this, if it's already enabled in /etc/bash.bashrc and /etc/profile # sources /etc/bash.bashrc). if ! shopt -oq posix; then if [ -f /usr/share/bash-completion/bash_completion ]; then . /usr/share/bash-completion/bash_completion elif [ -f /etc/bash_completion ]; then . /etc/bash_completion fi fi
if [ -e $HOME/.bash_functions ]; then source$HOME/.bash_functions fi
.bash_functions
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functioncd() { DIR="$*"; # if no DIR given, go home if [ $# -lt 1 ]; then DIR=$HOME; fi; builtincd"${DIR}" && \ # use your preferred ls command ls -F --color=auto }
.bash_aliases
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alias gh='history|grep' alias cpv='rsync -ah --info=progress2' alias ..='cd ..' alias ...='cd ../..' alias untar='tar -zxvf ' alias pg='ps -aux|grep ' woc_he() { curl -s "https://ipinfo.io/${1:-}" echo }
if [ ! -x "$doiido"]; then mkdir"$doiido" chmod +x "$doiido" fi
4.是判断变量$doiido是否有值
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if [ ! -n "$doiido" ]; then echo"$doiido is empty" exit 0 fi
5.两个变量判断是否相等
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if [ "$var1" = "$var2" ]; then echo'$var1 eq $var2' else echo'$var1 not eq $var2' fi
6.测试退出状态：
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if [ $? -eq 0 ];then echo'That is ok' fi
7.数值的比较：
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if [ "$num" -gt "150" ];then echo"$num is biger than 150" fi
8.a>b且a<c
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(( a > b )) && (( a < c )) [[ $a > $b ]] && [[ $a < $c ]] [ $a -gt $b -a $a -lt $c ]
9.a>b或a<c
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(( a > b )) || (( a < c )) [[ $a > $b ]] || [[ $a < $c ]] [ $a -gt $b -o $a -lt $c ]
10.检测执行脚本的用户
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if [ "$(whoami)" != 'root' ]; then echo"You have no permission to run $0 as non-root user." exit 1; fi
上面的语句也可以使用以下的精简语句
1
[ "$(whoami)" != 'root' ] && ( echo"You have no permission to run $0 as non-root user."; exit 1 )
11.正则表达式
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doiido="hero" if [[ "$doiido" == h* ]];then echo"hello，hero" fi
8. ===其他例子===
1. 查看当前操作系统类型
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#!/bin/sh
SYSTEM=`uname -s` if [ $SYSTEM = "Linux" ] ; then echo"Linux" elif [ $SYSTEM = "FreeBSD" ] ; then echo"FreeBSD" elif [ $SYSTEM = "Solaris" ] ; then echo"Solaris" else echo"What?" fi
2. if利用read传参判断
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#!/bin/bash read -p "please input a score:" score echo -e "your score [$score] is judging by sys now" if [ "$score" -ge "0" ]&&[ "$score" -lt "60" ];then echo"sorry,you are lost!" elif [ "$score" -ge "60" ]&&[ "$score" -lt "85" ];then echo"just soso!" elif [ "$score" -le "100" ]&&[ "$score" -ge "85" ];then echo"good job!" else echo"input score is wrong , the range is [0-100]!" fi
3. 判断文件是否存在
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#!/bin/sh today=`date -d yesterday +%y%m%d` file="apache_$today.tar.gz" cd /home/chenshuo/shell
if [ -f "$file" ];then echo “”OK" else echo "error $file" >error.log mail -s "fail backup from test" loveyasxn924@126.com <error.log fi
4. 这个脚本在每个星期天由cron来执行。如果星期的数是偶数，他就提醒你把垃圾箱清理：
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#!/bin/bash WEEKOFFSET=$[ $(date +"%V") % 2 ] if [ $WEEKOFFSET -eq "0" ]; then echo"Sunday evening, put out the garbage cans." | mail -s "Garbage cans out" your@your_domain.org fi
#! /bin/sh dir_d=/media/disk_d dir_e=/media/disk_e dir_f=/media/disk_f a=`ls$dir_d | wc -l` b=`ls$dir_e | wc -l` c=`ls$dir_f | wc -l` echo"checking disk_d..." if [ $a -eq 0 ]; then echo"disk_d is not exsit,now creating..." sudo mount -t ntfs /dev/disk/by-label/software /media/disk_d else echo"disk_d exits" fi echo"checking disk_e..." if [ $b -eq 0 ]; then echo"disk_e is not exsit,now creating..." sudo mount -t ntfs /dev/disk/by-label/elitor /media/disk_e else echo"disk_e exits" fi echo"checking disk_f..." if [ $c -eq 0 ]; then echo"disk_f is not exsit,now creating..." sudo mount -t ntfs /dev/disk/by-label/work /media/disk_f else echo"disk_f exits" fi
Module Overview: The ahb_sfr module is designed to interface with a system’s Special Function Registers (SFRs) via the AHB (Advanced High-performance Bus). It primarily handles the reading and writing operations to these registers based on external requests. The module synchronizes these requests and manages data transfer between the external bus and the internal registers, ensuring data integrity and proper timing.
Timing control:
2. Input/Output Interfaces Descriptions:
Inputs:
sfrclk: The clock signal for the module. All synchronous operations are triggered on the rising edge of this clock.
sfrrstz: Active low reset signal. When asserted, it initializes the module’s internal registers and logic.
sfrdatai [7:0]: Data input from the SFRs to be sent to the external bus.
ADDR [14:0]: Address bus input specifying the SFR address for the current operation.
DATA [7:0]: Data bus input specifying the data to be written to the SFRs.
REQ: Request signal indicating an active read or write operation.
WR: Write enable signal indicating if the current operation is a write (asserted) or read (deasserted).
Outputs:
sfrwe: Write enable output that signals whether a write operation should be performed to the SFRs.
sfraddr (output wire [14:0]): Address output that mirrors the input address to the SFRs.
sfrdatao [7:0]: Data output holding the data to be written to the SFRs.
s2adata [7:0]: Data output that directly mirrors the input sfrdatai, intended for external monitoring or further processing.
ACK: Acknowledge signal toggled to indicate the completion of a request processing cycle.
3. Clock and Reset Strategy:
Clock:
Name: sfrclk
Active State: The clock signal is active on the rising edge, which is used to synchronize all sequential logic within the module.
Reset:
Name: sfrrstz
Active State: The reset signal is active-low. When asserted, it initializes the module’s internal registers and logic.
4-1. Parameters constant:
None
4-2. Macro constant:
None
5. Algorithmic Logic
Reset and Initialization: All internal registers (ReqSyncD, SFRWrS, data_i, wr_i, addr_i, sfrwe, sfrdatao, and ACK) are initialized to their default states upon reset (sfrrstz asserted).
Request Synchronization: The module uses a simple synchronization mechanism to detect edges in the REQ signal. This is achieved by comparing the current REQ state with a delayed version (ReqSyncD), stored from the previous clock cycle. The result (ReqToggle) indicates a change in the request state, triggering data and control updates.
Data and Control Flow: Upon detecting a request (ReqToggle asserted), the module captures the address (ADDR), data (DATA), and write enable (WR) from the inputs and stores them in internal registers (addr_i, data_i, wr_i). These values are used to set up the subsequent operations.
If a write operation is detected (wr_i asserted), the write enable output (sfrwe) is set based on the SFRWrS status, which tracks the request state to prevent erroneous writes during request transitions.
For write operations, the data to be written to the SFR (sfrdatao) is updated with the value from data_i if both wr_i and SFRWrS are asserted.
Output and Acknowledgement: The address output (sfraddr) directly mirrors the internal address register (addr_i). The s2adata output is a direct pass-through of the sfrdatai input, allowing external entities to monitor or process the incoming SFR data. The ACK signal is toggled to indicate the completion of a processing cycle, helping external controllers to manage the timing and sequence of operations.
6 Operational Cycles
The ahb_sfr module is designed to interface with a system bus, handling specific register operations including data transfer and synchronization. The module operates primarily on the rising edge of the system clock (sfrclk) and remains sensitive to the active low reset signal (sfrrstz). The core functionality revolves around capturing and responding to data requests from the bus, managing data write operations, and acknowledging the completion of these operations.
Sequential Logic:
Reset and Synchronization: The module uses edge-triggered flip-flops to capture and synchronize the request signal (REQ). This synchronization helps in mitigating any metastability issues due to the asynchronous nature of the input request.
Data and Control Signal Capturing: Upon detecting a change in the request signal (ReqToggle), the module captures the address (ADDR), data (DATA), and write control signal (WR) from the bus. These captured values are stored in internal registers (addr_i, data_i, wr_i) and are used in subsequent operations.
Write Enable Logic: The write enable signal (sfrwe) is controlled based on the write request (wr_i) and the synchronization status (SFRWrS). This ensures that write operations are only enabled under valid conditions.
Data Output and Acknowledgment: The module outputs data (sfrdatao) and toggles the acknowledgment signal (ACK) based on the internal state and the synchronization of the request.
Combinational Logic:
Request Toggle Detection: A simple XOR gate detects changes in the request signal, generating a toggle signal (ReqToggle) that triggers data capturing and acknowledgment logic.
Data Output to System Bus: The output data to the system bus (s2adata) is directly driven by the input data from another source (sfrdatai), indicating a simple combinational pathway.
7. Data Flow
ReqSyncD (Request Synchronized Delayed): This signal holds the delayed version of the external request signal (REQ). It is used to detect edges in the request signal by comparing its current state to its previous state.
data_i (Data Input Register): Captures the data from the bus when a new request is detected. This register temporarily holds the data for processing or forwarding during the write operations.
SFRWrS (SFR Write Synchronize): Indicates the synchronization status for write operations. It is set when a new request is detected and used to control the write enable signal.
wr_i (Write Input Register): Captures the write control signal from the bus, indicating whether the current operation involves writing data to the register.
addr_i (Address Input Register): Holds the address from the bus where data needs to be written or read, captured upon a new request.
ReqToggle (Request Toggle): A signal generated by XORing the current and delayed request signals. It indicates a change in the request status, used to trigger data capturing and acknowledgment logic.
sfrwe (SFR Write Enable): Controlled by the write request and synchronization status, this signal enables the data write operation to the internal registers.
sfrdatao (SFR Data Output): Outputs data based on the internal logic conditions, specifically during write operations when both write request and synchronization are affirmed.
ACK (Acknowledgment): Toggled in response to a new request detection, signaling the completion of a data read or write operation.
Module Overview: The ct_pmp_regs module is designed to manage and configure a set of registers related to physical memory protection (PMP) in a processor. The primary objective of this module is to handle the read and write operations to PMP configuration and address registers. It ensures that the PMP settings are correctly updated based on control signals, allowing for secure and controlled access to memory regions. The module supports multiple PMP entries, each with configurable attributes such as read, write, execute permissions, address mode, and lock status.
Timing control:
2. Input/Output Interfaces Descriptions:
Inputs:
cp0_pmp_wdata [63:0]: A 64-bit data bus used to write data into the PMP configuration and address registers.
cpuclk: The clock signal for synchronizing operations within the module.
cpurst_b: An active-low reset signal used to initialize the module’s registers to their default states.
pmp_csr_sel [17:0]: An 18-bit signal used to select which PMP configuration or address register is being accessed.
pmp_csr_wen [17:0]: An 18-bit write enable signal used to control the write operations to the PMP registers.
Outputs:
pmp_cp0_data [63:0]: A 64-bit data bus used to output data from the PMP configuration and address registers.
pmpaddr0_value [28:0] to pmpaddr7_value [28:0]: Eight 29-bit signals representing the values of the PMP address registers.
pmpcfg0_value [63:0]: A 64-bit signal representing the combined values of the first four PMP configuration registers.
pmpcfg2_value [63:0]: A 64-bit signal representing the combined values of the next four PMP configuration registers.
3. Clock and Reset Strategy:
Clock:
Name: cpuclk
Active State: The clock signal is active on the rising edge, which is used to synchronize all sequential logic within the module.
Reset:
Name: cpurst_b
Active State: The reset signal is active-low. When asserted (logic 0), it initializes all PMP configuration and address registers to their default states, ensuring a known starting condition for the module.
4-1. Parameters constant:
The module contains the following parameter constant:
parameter ADDR_WIDTH = 29;
4-2. Macro constant:
None
5. Algorithmic Logic
Configuration Registers:
The module contains multiple configuration registers (pmpcfg) which store permissions and attributes such as readable, writable, executable, and locked states.
Each configuration register manages separate regions or segments of memory, with specific fields determining the operation mode and permissions of each segment.
PMP Initialization:
Upon reset (cpurst_b signal low), all the configuration and address registers within the module are initialized to a predefined state (0), ensuring a secure and known initial state.
Permission and Mode Settings:
Each PMP configuration register (pmpcfgX) holds bits that define access rights: readable, writable, and executable, alongside a two-bit mode for address matching.
The lock bit in each configuration register indicates whether further writes to the register are possible.
Hardware Updates:
Configuration registers are updated on the rising edge of the clock (cpuclk) when the corresponding write enable (pmp_csr_wen) signals are valid and no lock conditions are met.
Address registers are updated similarly, respecting any lock and match-mode dependencies ensuring secure modification prevention.
Chaining Logic:
Address matching and permission interpretation rely on the state of the configuration registers, such as mode matching and lock conditions.
For chained configurations, the write operations to a PMP address are conditional on already established locks and address mode values.
Inter-module Communication:
Input cp0_pmp_wdata carries the data for register updates, while pmp_cp0_data serves as an output conveying PMP configurations to other modules.
Selection and enable vectors (pmp_csr_sel, pmp_csr_wen) control which registers are accessed for read/write operations.
6 Operational Cycles
Reset Phase: Registers are reset, meaning they all initialize to zero, ensuring that all regions are initially inaccessible until explicitly configured.
Configuration Phase: During normal operation post-reset, configuration registers can be updated based on provided data (cp0_pmp_wdata) when writing is enabled via control signals and existing register contents permit the modification (e.g., no active lock bits).
Normal Operation: During normal runtime, the PMP registers govern access permissions dynamically, allowing secure and managed access to the processor’s memory space per the configuration stored within these registers. Algorithm Mechanics:
Registers: The module contains various configuration registers (pmp0cfg, pmp1cfg, … , pmp7cfg) and address registers (pmpaddr0_value through pmpaddr7_value) to manage PMP regions.
Configuration Logic:
Each pmpcfg# register has fields for address matching mode, permissions (readable, writable, executable), and a lock bit to prevent further modifications.
Data from cp0_pmp_wdata is loaded into registers based on write enable signals (pmp_csr_wen[]) provided that the lock bit is not set.
Address Logic:
Address registers are updated based on corresponding enable signals ensuring the previous entry is not locked.
Timing: Updates to the registers are synchronized with the clock signal. On a rising edge of cpuclk, updates occur if the write enable (pmp_csr_wen[]) is set and the reset (cpurst_b) is not asserted.
7. Data Flow
Data Tracing and Processing:
Input to Register Update: Data from cp0_pmp_wdata is stored into the appropriate configuration (pmpcfg#) or address (pmpaddr#_value) register based on the current state of selection and enable signals, considering lock conditions.
Configuration to Output: The corresponding configuration or address states can be read out via pmp_cp0_data or pmpcfg0_value, based on pmp_csr_sel[].
Error Handling:
Lock Protection: If a lock bit within a configuration register is set, further writes to that configuration are blocked regardless of the enable state.
Timing in Data Movement:
Sequential Updates: Data from cp0_pmp_wdata is sequentially applied across cycles, starting with the first enabled register according to the selection and enable signals.
Concurrency Management:
Independent Configuration Blocks: Each pmpcfg# and pmpaddr# register set operates independently, allowing updates to different regions concurrently, as long as they adhere to lock and enable conditions.
// Instantiate the Unit Under Test (UUT) multiply uut ( .clk(clk), .mult_begin(mult_begin), .mult_op1(mult_op1), .mult_op2(mult_op2), .product(product), .mult_end(mult_end) ); integer i,errors[0:39],cnt; integer fd = 0; initialbegin // Initialize Inputs clk = 0; mult_begin = 0; mult_op1 = 0; mult_op2 = 0; for (i = 0; i < 40; i = i + 1) begin errors[i] = 0; end i=0; cnt=0; $dumpfile("mul.vcd");
$dumpvars(); fd = $fopen("./report.txt", "w"); // if(!fd) // begin // $display("Could not open File \r"); // $stop; // end
#500; if (cnt == 0) begin $display("Simulation finished Successfully."); $fdisplay(fd, "Simulation finished Successfully."); end elseif (cnt >= 1) begin $display("%0d ERROR! See log for details.",cnt); $fdisplay(fd, "%0d ERROR! See log above for details.",cnt) ; end $fclose(fd);
// $finish; end always #5 clk = ~clk;
//比较 always @ (negedge mult_end) begin if ( product !== Data_in_t || product == 64'Bz ) begin // $display(" ------ERROR. A mismatch has occurred-----,ERROR in ", i); $fdisplay(fd," ------ERROR. A mismatch has occurred-----,ERROR in ", i); errors[i-1] = 1; cnt = cnt + 1; end i = i + 1; end endmodule
assign mult_end = mult_valid & ~(|multiplier); // End signal: when multiplier is all zeros always @(posedge clk) begin if (multiplier == 32'd0) begin mult_valid <= 1'b0; // No valid multiplication operation end else begin mult_valid <= 1'b1; end end
// Absolute values of operands wire op1_sign; // Sign of operand 1 wire op2_sign; // Sign of operand 2 wire [31:0] op1_absolute; // Absolute value of operand 1 wire [31:0] op2_absolute; // Absolute value of operand 2 assign op1_sign = mult_op1[31]; assign op2_sign = mult_op2[31]; assign op1_absolute = op1_sign ? (~mult_op1+1) : mult_op1; assign op2_absolute = op2_sign ? (~mult_op2+1) : mult_op2;
// Loading multiplicand and shifting reg [63:0] multiplicand; always @ (posedge clk) begin if (mult_valid) begin// Shift multiplicand left by one bit each clock cycle multiplicand <= {multiplicand[62:0],1'b0}; end elseif (mult_begin) begin// Load multiplicand with absolute value of operand 1 multiplicand <= {32'd0,op1_absolute}; end end
// Loading multiplier and shifting always @ (posedge clk) begin if(mult_valid) begin// Shift multiplier right by one bit each clock cycle multiplier <= {1'b0,multiplier[31:1]}; end elseif(mult_begin) begin// Load multiplier with absolute value of operand 2 multiplier <= op2_absolute; end end
// Accumulator for the product reg [63:0] product_temp; always @ (posedge clk) begin if (mult_valid) begin product_temp <= product_temp + partial_product; end elseif (mult_begin) begin product_temp <= 64'd0; end end
// Product sign and final result reg product_sign; // Sign of the product always @ (posedge clk) begin if (mult_valid) begin product_sign <= op1_sign ^ op2_sign; // Calculating sign of the product end end assign product = product_sign ? (~product_temp+1) : product_temp; // Adjusting sign of the product endmodule
3 Report
3.1 Compile Report
Errors: 0, Warnings: 0
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Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 Start time: 17:33:09 on Jan 26,2024 vlog -work work ./design/testbench.v ./design/updated_design_0.v -l vcompile.txt -- Compiling module tb -- Compiling module multiply
Top level modules: tb End time: 17:33:09 on Jan 26,2024, Elapsed time: 0:00:00 Errors: 0, Warnings: 0
# vsim -voptargs="+acc" work.tb -l ./vsim.txt -wlf ./vsim.wlf # Start time: 17:33:09 on Jan 26,2024 # ** Note: (vsim-8009) Loading existing optimized design _opt2 # // ModelSim SE-64 10.7 Dec 7 2017 # // # // Copyright 1991-2017 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim SE-64 and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading work.tb(fast) # Loading work.multiply(fast) # Simulation finished Successfully. # quit # End time: 17:33:10 on Jan 26,2024, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0
// Instantiate the Unit Under Test (UUT) multiply uut ( .clk(clk), .mult_begin(mult_begin), .mult_op1(mult_op1), .mult_op2(mult_op2), .product(product), .mult_end(mult_end) ); integer i,errors[0:39],cnt; always #5 clk = ~clk;
endmodule
3 Log
3.1 Compile Log
Errors: 0, Warnings: 0
1 2 3 4 5 6 7 8 9 10
Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 Start time: 20:07:49 on Dec 01,2023 vlog -work work ./design/multiply.v ./design/testbench.v -l vcompile.txt -- Compiling module multiply -- Compiling module tb
Top level modules: tb End time: 20:07:49 on Dec 01,2023, Elapsed time: 0:00:00 Errors: 0, Warnings: 0
# vsim -voptargs="+acc" work.tb -l ./vsim.txt -wlf ./vsim.wlf # Start time: 20:07:49 on Dec 01,2023 # ** Note: (vsim-8009) Loading existing optimized design _opt2 # // ModelSim SE-64 10.7 Dec 7 2017 # // # // Copyright 1991-2017 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim SE-64 and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading work.tb(fast) # Loading work.multiply(fast) # ------ERROR. A mismatch has occurred-----,ERROR in 40 # 1 ERROR! See log above for details. # quit # End time: 20:07:50 on Dec 01,2023, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0
3.3 TestBench Output
1 2
------ERROR. A mismatch has occurred-----,ERROR in 40 1 ERROR! See log above for details.
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